The fabrication and packaging of integrated circuit devices (ICs) is a complicated process. An IC is created by fabricating hundreds or thousands of devices onto a silicon wafer. Each device (die) is then packaged and used as a component in a larger electronic system. In such a complicated manufacturing process thousands of data points are recorded at different stages of the process and it is critical that engineers can analyze and correlate this data.
The critical dimensions of the devices—for example thicknesses and lengths—are measured during the fabrication process and are commonly referred to as INLINE parameters. The electrical characteristics of the wafer are tested at WAT (Wafer Acceptance Test, otherwise known as “ETEST”) using test structures in the die periphery. Finally, the functionality and performance of each die is tested at WAFER SORT. The purpose of INLINE and WAT is primarily data collection, however during WAFER SORT die are “binned” into categories which include many different pass and fail bins. The nature of the pass or failure characterizes the die and dictates which bin number is assigned. The testing of application specific integrated circuits (ASICs) is well established, however the testing of programmable logic devices (PLDs)—for example, field programmable gate arrays (FPGAs)—is a little more complex and involves additional testing since PLDs may be programmed with many different user designs. For instance, in SRAM-based FPGAs a readback test is done to verify the basic functionality of the configuration memory cells while additional patterns test if the device will work under thousands of different configurations. Die which fail either readback or one of the many functional patterns will be assigned a bin depending on which test it fails first (“stop-at-fail testing”). In addition to pass/fail data, WAFER SORT also includes performance testing where passing die are sorted into bins by device speed (performance). The bin number (good or bad) is logged to a data file with X and Y coordinates identifying the location of each die on the wafer. The wafer is then sawn and each die is packaged and tested once again at FINAL TEST to guaranteed specification limits. IINLINE, WAT and WAFER SORT data is collected at ambient temperature while FINAL TEST is conducted at elevated temperatures. During all of these steps, data is logged and collected for analysis. Note that the description of these tests is not intended to be comprehensive, but gives some indication of the tests performed and data collected during the IC manufacturing process.
In order to improve the manufacturing process of ICs in general, such as reducing defects, the manufacturing data is collected and analyzed. Conventional commercial tools such as the dataPOWER™ product from PDF Solutions, Inc (see http://dp.pdf.com/site/products/dpc_core.html) or the dataConductorEP product from Syntricity, Inc. of San Diego, Calif. (see http://www.syntricity.com/Products/o_datace.htm) takes data from throughout the manufacturing process (from fabrication to final test), aligns, organizes and stores the data in a database, and displays the data in order to allow users to analyze yield and production issues quickly.
While the above conventional commercial tools are useful, many are typically for ASICs, client-server based with a platform dependent fab client, or limited to data from one manufacturer. Thus there is a need for an improved software tool that automatically collects and integrates data from multiple IC manufacturers and allows real-time access to reports and charts generated from the data.